Not applicable.
This invention is in the field of semiconductor integrated circuits, and is more specifically directed to techniques for protecting integrated circuits from damage caused by electrostatic discharge.
Modern high-density integrated circuits are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body (human or otherwise) as it physically contacts an integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor, or MOS, context).
It is often difficult to analyze the ESD vulnerability of a given integrated circuit, because the charge versus time characteristics of ESD events vary quite widely among the various sources of ESD. In fact, the ESD protection of modern integrated circuits is characterized according to multiple models, each of which are intended to model a type of ESD. The Human Body Model (HBM) models discharge of a charged human contacting an integrated circuit, and is realized by a 150 pF capacitance discharging into the integrated circuit within about 100 nsec. The Machine Model (MM) models discharge from metal objects such as test and manufacturing equipment, and generally uses a higher capacitance with lower internal resistance than the HBM, resulting in even faster discharge times. The Charged Device Model (CDM) models a discharge from a charged integrated circuit to ground, rather than a discharge to the integrated circuit. These differences in discharge characteristics and polarity manifest themselves in different failure manifestations within the integrated circuit; indeed the conduction may follow different paths within the device.
To avoid damage from ESD, modern integrated circuits incorporate ESD protection devices at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path, so that the brief but massive ESD charge may be safely conducted away from structures that are not capable of handling the event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large p-n junction capable of conducting the ESD charge. Inputs and outputs, on the other hand, typically have a separate ESD protection device added in parallel to the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event, with large conduction capability, but remains off and presents no load during normal operation.
Examples of ESD protection devices are well known in the art. In the case of MOS technology, an early ESD protection device was provided by a parasitic thick-field oxide MOS transistor that was turned on by and conducted ESD current, as described in U.S. Pat. No. 4,692,781 and in U.S. Pat. No. 4,855,620, both assigned to Texas Instruments Incorporated and incorporated herein by this reference. As the feature sizes of MOS integrated circuits became smaller, and with the advent of complementary MOS (CMOS) technology, the most popular ESD protection devices utilized a parasitic bipolar device to conduct the ESD current, triggered by way of a silicon-controlled-rectifier (SCR) structure, as described in Rountree et al., xe2x80x9cA Process-Tolerant Input Protection Circuit for Advanced CMOS Processesxe2x80x9d, 1988 EOS/ESD Symposium, pp. 201-205, incorporated herein by this reference, and in U.S. Pat. No. 5,012,317 and U.S. Pat. No. 5,907,462, both assigned to Texas Instruments Incorporated and also incorporated herein by this reference.
It has been observed that changes in integrated circuit manufacturing technology often necessitate changes in the ESD protection scheme, generally because the process changes alter the ability of the ESD protection devices to operate. The silicide cladding of junctions and the incorporation of shallow trench isolation (STI) have been observed to reduce the gain of the parasitic bipolar device in the SCR protection scheme, preventing proper triggering and conduction. The effects of these process changes are exacerbated by the continuing trend toward smaller device feature sizes, both laterally and vertically, rendering the devices ever more fragile to ESD.
However, the continued progression toward smaller device sizes has not, in many cases, relaxed the voltage requirements of integrated circuit terminals. For example, a modern manufacturing process fabricates transistors having 0.18 xcexc channel lengths, with a gate dielectric thickness of 7 nm or less, for use in integrated circuits that must still tolerate operating voltages of up to 7 volts at input/output terminals. Many integrated circuits are also required to have xe2x80x9cfailsafexe2x80x9d inputs and outputs, meaning that the terminal cannot be clamped to any power supply rail, so that large currents are not conducted from terminal voltages when the device is in an xe2x80x9coffxe2x80x9d state. The xe2x80x9cfailsafexe2x80x9d constraint is especially important in multi-voltage systems in which the inputs and outputs are power sequenced.
The high operating voltage and failsafe design constraints have been addressed through the use of drain-extended MOS transistors (referred to as DE, DEMOS, or DENMOS in the case of n-channel devices). A conventional DE transistor has its drain region located within a well of the same conductivity type; for example, in the n-channel case, the n-type drain region is placed within a relatively lightly-doped n-type well. The increased drain-to-substrate junction area provided by the well, along with the reduced dopant concentration at the drain-to-substrate junction, greatly increases the junction breakdown voltage, permitting high voltage operation of the transistor while tolerating voltage excursions at the drain that can occur in the absence of a clamp. DEMOS transistors also enable the use of thinner gate oxide, because the voltage drop across the depletion region of the well reduces the electric field at the drain-side edge of the gate oxide, and thus reduces the number of channel xe2x80x9chotxe2x80x9d carriers that are produced. This reduction in xe2x80x9chotxe2x80x9d carrier effects, specifically threshold voltage shift, enables the construction of reliable transistors with extremely thin gate oxides. DEMOS devices also present high output impedance, which is especially attractive in using the device in analog circuits. DEMOS transistors are therefore very attractive for use at input/output terminals of modern integrated circuits.
It has been observed, however, that DEMOS devices themselves provide very poor inherent ESD protection. Referring to FIG. 1a, plot 2 illustrates source-drain current versus drain-to-source voltage for DENMOS transistor 6 (FIG. 1b), with the gate grounded as shown in FIG. 1b. Plot 2 represents actual measurements of transistor 6, of drain-extended construction to have an effective channel length of 0.64 xcexc and a channel width of about 50 xcexc, measured from a sequence of 100 nsec pulses of increasing voltage applied to the drain of transistor 6. As shown by plot 2 of FIG. 1a, drain avalanche breakdown of transistor 6 occurs at about 13 volts drain-to-source-voltage. Unlike conventional ESD protection devices, however, there is no parasitic lateral npn bipolar conduction in transistor 6, and thus no xe2x80x9csnapbackxe2x80x9d region in characteristic plot 2 (as shown by the ideal plot 2xe2x80x3 in FIG. 1a). Instead, a relatively high xe2x80x9conxe2x80x9d resistance of about 20 ohms is evident, with conduction continuing until about 17 volts, at which point thermal runaway causes device failure (evident by the knee in plot 2 at that point). While gate-coupled DENMOS devices have exhibited some snapback in their characteristic, it has been found that the failure current (i.e., the thermal runaway point in the characteristic) does not scale with channel width in these DENMOS devices. The failure mechanism in these devices has also been observed to be non-uniform conduction, from localized breakdown.
The protection of DENMOS devices by way of an SCR structure in combination with a grounded gate DENMOS device has been described in Kunz et al., xe2x80x9c5-V Tolerant Fail-safe ESD Solutions for 0.18 xcexcm Logic CMOS Processxe2x80x9d, ESD/EOS Symposium (Sep. 11, 2001), incorporated herein by this reference, and is illustrated, in cross-section, in FIG. 2a. In this example, DENMOS transistor 9 is in parallel with SCR 11. Source region 12 of transistor 9 is connected to ground, while drain 14 is located within n-well 10, and is connected to anode A of SCR 11 along with p+region 16. P+ region 16 and n+ drain region 14 are separated from one another by shallow trench isolation structure 15, which is typically silicon dioxide deposited into a shallow trench. P+ region 16 is also located within n-well 10, as is a portion of n+ trigger region 18 in SCR 11. Cathode K of SCR 11 is biased to ground, and is connected to n+ region 20, which is disposed within p-type substrate 8 along with source region 12. Each of heavily-doped regions 12, 14, 16, 18, 20 are clad with metal silicide film 28, as are other diffused regions within the same integrated circuit, for improved conductivity. In this structure of FIG. 2a, the blocking of silicide formation is effected by nitride structures 22 and polysilicon gate 24, formed by conventional photolithography and patterned etches. Gate 24 is of course the gate electrode for DENMOS transistor 9, and its nitride structures 22 are sidewall filaments formed in the usual manner. More specifically, nitride structures 22 between p+ region 16 and n+ region 18 blocks the formation of silicide and also blocks the source/drain implants, but since these structures 22 are not adjacent gate polysilicon 24, the formation of these blocking nitride structures 22 requires an additional photolithography and etching step.
FIG. 2b is an electrical schematic of the structure of FIG. 2a, in its role as an ESD protection device. SCR 11 includes npn transistor 11n and pnp transistor 11p, with the collector of transistor 11p connected to the base of transistor 11n by the resistance through substrate 8. Transistor 11p has p+ region 16 as its emitter, n-well 10 as its base, and substrate 8 as its collector. Transistor 11n of SCR 11 has n+ region 20 as its emitter, n+ region 18 as its collector and as the trigger for SCR 11, and substrate 8 as its base. In operation, SCR 11 is triggered by the forward biasing of the emitter-base junction of transistor 11p. This forward-bias current enters n+ region 18, and causes breakdown of the junction between n+ region 18 and substrate 8, in turn triggering bipolar conduction by transistor 11n. As described in the Kunz et al. article, the voltage at which n+ region triggers the SCR action depends on strongly on the width of the channel between n+ regions 18, 20 that underlies nitride structure 22.
Because of the conductivity of n-well 10, the collector current of transistor 11p becomes base current for the parasitic npn transistor 9n of DENMOS transistor 9, causing this device to conduct. The parasitic bipolar transistor 9n at DENMOS transistor 9 thus assists in the dissipation of the charge presented to anode A through n+ source region 12, which serves as secondary cathode SK. The structure of FIG. 2a thus has been found to provide good ESD protection.
However, the structure of FIG. 2a requires the blocking of silicide and shallow trench isolation formation, specifically by requiring an additional photolithography operation to form nitride structures 22. This additional process step of course adds significant manufacturing cost to the integrated circuit embodying the structure. In addition, it has been observed that the structure of FIG. 2a is not suitable for use in connection with terminals, such as power supply terminals, at which a low output impedance is required.
By way of further background, U.S. Pat. No. 5,940,258, assigned to Texas Instruments Incorporated and incorporated herein by this reference, describes an ESD protection circuit in which a portion of the energy from the ESD pulse itself is used to bias the substrate of the protection circuit. Specifically, this diverted energy raises the substrate bias voltage in the vicinity of the primary discharge device, facilitating its bipolar conduction of the ESD energy. This substrate bias improves the response of the ESD protection device, while not affecting normal operation of the integrated circuit. According to this approach, a capacitor is used to provide the substrate bias current. However, the use of a capacitor as a primary element in an ESD protection device is not favored in integrated circuits using extremely thin gate dielectric films, having thicknesses of 7 nm or less.
It is therefore an object of this invention to provide an electrostatic discharge (ESD) protection structure that is suitable for use in connection with drain-extended metal-oxide semiconductor (DEMOS) fabrication technology.
It is a further object of this invention to provide such a structure which can be easily fabricated without requiring an additional photolithography operation.
It is a further object of this invention to provide such a structure that is compatible for use in connection with low impedance terminals of the integrated circuit.
It is a further object of this invention to provide such a structure that is compatible for integrated circuits fabricated according to high density and high integration technologies, including extremely thin gate dielectric layers, silicide cladding, and shallow trench isolation.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented as a pair of drain-extended MOS devices, both having drains coupled to the terminal being protected. One of the devices serves as a substrate pump device, and is fabricated so that its extended drain underlies its gate electrode, establishing a significant gate to drain capacitance that couples ESD energy to gates of the drain-extended MOS devices. As the pump device is turned on, it conducts current to the body node, or channel, of the second drain-extended device, forward-biasing the base-emitter junction of the parasitic bipolar transistor in the protection DEMOS device, initiating bipolar conduction and safely conducting the ESD energy to ground. A control circuit is provided to ensure that the pair of DEMOS devices are turned off during normal operation.